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SPL11A Programming Guide
V0.1 - Oct. 23, 2002
Technology for easy living
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. However, SUNPLUS Contact SUNPLUS No
TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. parties which may result from its use.
responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
19, Innovation Road 1 * Science-Based Industrial Park * Hsin-Chu * Taiwan * R.O.C.
886-3-578-6005
886-3-578-4418
fae@sunplus.com.tw
www.sunplus.com.tw
PRELIMINARY
SPL11A PROGRAMMING GUIDE
0 Table of Content
0 1 2 TABLE OF CONTENT ..................................................................................................................................... 2 REVISION HISTORY ....................................................................................................................................... 5 INTRODUCTION .............................................................................................................................................. 6 2.1 GENERAL DESCRIPTION ............................................................................................................................ 6 2.2 FEATURE ................................................................................................................................................. 6 2.3 APPLICATION............................................................................................................................................ 7 2.4 STRUCTURE DIAGRAM............................................................................................................................... 8 3 MEMORY ......................................................................................................................................................... 9 3.1 MEMORY MAPPING ................................................................................................................................... 9 3.2 MEMORY LOCATION................................................................................................................................. 10 3.3 VECTOR ................................................................................................................................................ 10 3.4 ERROR-ADDRESS AREA ........................................................................................................................... 10 3.5 EXAMPLE ............................................................................................................................................... 10 4 CPU CLOCK CONTROL ................................................................................................................................11 4.1 CLOCK SOURCE CONTROL .......................................................................................................................11 4.1.1 Clock sources combination (OTP)..........................................................................................11 4.2 CPU CLOCK CONTROL REGISTER ............................................................................................................11 4.2.1 P_05H_CPU_CLK ($0005): set CPU clock..........................................................................11 5 IO AND RFC FUNCTION ............................................................................................................................... 12 5.1 PORTA(IOA) CONTROL REGISTER ........................................................................................................... 12 5.1.1 P_00H_IOA_Data ($0000): Data register of PortA ................................................................ 12 5.1.2 P_01H_IOA_Dir ($0001): Direction Control register of PortA ................................................ 12 5.1.3 P_02H_IOA_Attrib ($0002): Attribute data register of PortA.................................................. 12 5.2 RESISTOR TO FREQUENCY CONVERTER (RFC) FUNCTION.......................................................................... 14 5.2.1 P_13H_RFC_CTL ($0013): RFC Control Register ............................................................ 14 5.2.2 How to use RFC function....................................................................................................... 15 5.2.3 Function description of PortA(IOA[7:0])................................................................................. 15 5.2.4 IOA Structure......................................................................................................................... 16 5.3 PORTB(INB) CONTROL REGISTER ........................................................................................................... 18 5.3.1 P_03H_INB_Data ($0003)..................................................................................................... 18
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SPL11A PROGRAMMING GUIDE 5.3.2 P_10H_IO_Config ($0010) .................................................................................................... 18 5.3.3 INB Structure......................................................................................................................... 19 6 SYSTEM CONTROL ...................................................................................................................................... 20 6.1 SYSTEM CONTROL.................................................................................................................................. 20 6.1.1 P_0FH_SYS_SWITCH ($000F) ............................................................................................ 20 6.1.2 P_0FH_SYS_SWITCH ($000F) ............................................................................................ 21 6.2 RESET FLAGS ........................................................................................................................................ 22 6.2.1 P_12H_RST_FG ($0012) ...................................................................................................... 22 7 TIMER/COUNTER ......................................................................................................................................... 23 7.1 TIMER STRUCTURE ................................................................................................................................. 23 7.2 TIMER SETUP & INITIALIZATION ................................................................................................................ 23 7.2.1 P_09H_TIMER_SET ($0009): Set the timer/counter configuration ....................................... 23 7.3 TIMER/INTERRUPT CLOCK SOURCES ........................................................................................................ 24 A. HSCK sources for timer, interrupt ................................................................................................ 24 7.3.1 P_0CH_TIMER_INT1 ($000C) .............................................................................................. 24 B. LSCK(32768) sources for timer, interrupt sources ................................................................... 25
7.3.2 P_0DH_TIMER_INT2 ($000D) .............................................................................................. 25 7.4 TIMER DATA REGISTER............................................................................................................................ 26 7.4.1 P_0AH_TML_LATCH ($000A)............................................................................................... 26 7.4.2 P_0BH_TMH_LATCH ($000B) .............................................................................................. 26 8 LCD ................................................................................................................................................................ 27 8.1 LCD RAM MAPPING............................................................................................................................... 27 8.2 CONTROL REGISTERS.............................................................................................................................. 27 8.2.1 Port_LCD_CTL ($0004)......................................................................................................... 27 8.2.2 LCD clock control .................................................................................................................. 29 8.3 MULTIPLE FUNCTIONS (I/O, SEGMENT & COMMON SHARING) ....................................................................... 30 8.3.1 LCD dot & I/O ........................................................................................................................ 30 8.3.2 LCD mapping with dot resolution........................................................................................... 31 9 WAKEUP / INTERRUPT ................................................................................................................................ 32 9.1 WAKEUP/INTERRUPT STRUCTURE DIAGRAM .............................................................................................. 32 9.2 WAKEUP/INTERRUPT CONTROL REGISTERS ............................................................................................... 33 9.2.1 P_07H_WKU_SET ($0007)................................................................................................... 33 9.2.2 Port_WKU_CLR ($0008) ....................................................................................................... 34 9.2.3 P_0EH_INT_SET($000E)...................................................................................................... 34
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SPL11A PROGRAMMING GUIDE 10 REMOTE CONTROL ..................................................................................................................................... 36 10.1 REMOTE CONTROL MODULE DIAGRAM ........................................................................ ! 10.2 CONTROL REGISTERS.............................................................................................................................. 36 10.2.1 P_06H_DUTY_CTL ($0006).................................................................................................. 36 11 DEVELOPMENT SYSTEM ............................................................................................................................ 37 11.1 SPL11A SIMULATOR .............................................................................................................................. 37 11.2 OTP WRITER AND DEMO BOARD .............................................................................................................. 37 12 MASK/BONDING OPTION ............................................................................................................................ 39 12.1 MASK OPTIONS FOR ROM VERSION OF SPL11A ....................................................................................... 39 12.2 BONDING OPTIONS FOR OTP VERSION OF SPL11A ................................................................................... 39 12.3 DEFAULT STATUS OF PINS ........................................................................................................................ 39 13 APPENDIX ..................................................................................................................................................... 40 13.1 PORT AND MEMORY MAP......................................................................................................................... 40 13.2 OTP (QFP) PIN DESCRIPTION ............................................................................................................... 41
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SPL11A PROGRAMMING GUIDE
1 Revision History
Revision Date By Remark
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SPL11A PROGRAMMING GUIDE
2 Introduction
2.1 General Description
SPL11A, a 8-bit LCD micro-controller, contains LCD-drivers, one-time programmable (OTP) ROM, SRAM, I/O, timer/counter, PLL, audio/remote control out, resistor to frequency converter (RFC) function in a single chip. The SPL11A is designed to drive LCD directly and perform efficient controller function
as well as arithmetic function. With the on-chip crystal oscillator, real time clock can be easily achieved. For power savings, several power-down modes are controllable by software programming. The
SPL11A is designed to be used in low-power electronic products such as remote controller, home appliance, calculator, and general LCD controller, etc.
2.2
Feature
Built-in Sunplus 8-bit CPU (Compatible with full 6502 instruction sets) Working voltage: 2.4V ~ 5.5V Maximum CPU speed: 4MHz @ 2.4V in ROSC mode 8K-byte EPROM with parallel programming & verification 128 bytes SRAM 48 bytes dual-port SRAM for LCD buffers LCD bias: 1/2 bias, 1/3 bias, 1/4 bias LCD dots: 12x30 (360 dots), 11x30 (330 dots), 10x30 (300 dots), 9x32 (288 dots), 8x32 (256 dots), 5x32 (160 dots), 4x32 (128 dots), and 3x32 (96 dots) A 16-bit re-loadable timer/counter An 8-pin IOA (Input with pull-high, input with pull low, floating, output, N open drain, P open drain) IOB Inputs with key wakeup function & pull-low (4 inputs pins shared with LCD segments) Dual clock PLL/R-oscillator & 32768 CPU Clock: PLL/2, PLL/4, PLL/8, PLL/16, 32768 PLL clock = 32768 * 37 * 4 = 4,849,664Hz; Maximum CPU clock in PLL clock mode: 4849664/2 = 2,424,832Hz Four Operating modes: Operating, Wait, Halt, and Standby modes Interrupt sources: 37.9K/N, 32768/N, TMO, EXT0, EXT1, T2Hz, and KEYC. Seven wakeup sources Built-in RFC (Resistor to Frequency Converter) function Reset flags: watchdog, error address, power-on, external reset, low voltage Watchdog reset and error-address reset are always enabled and will reset CPU if these events
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SPL11A PROGRAMMING GUIDE occur Low voltage reset can be disabled by LVROFF pin Wakeup start from reset or next instruction Low voltage reset level: 2.4V The pin assignment of ROM version will be the same as in OTP version, except PIE, VDDT, VPP,
HCKOPT, LCKOPT, LVROFF, and TEST pins
2.3
Application
Remote controller with LCD ability. LCD controller for home appliance. Watch, calendar, calculator, etc.
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2.4
Structure Diagram
IOA & INB
ROSC/VCOIN, PLL/ROSC, CPU Clock, OPT_ROSC_PLL, RESET LVR
IOA0 ~ IOA7
INB0 ~ INB7
32768Hz related clock & charge pump
X32I, X32O, V1, V2, V3 CUP1, CUP2, CUP3, CUP4, OPT_X32K_R32K
CPU15
ADDRES S
D0 ~ D7
Timer/Counter
DC0 ~ DC7
ED0 ~ ED7 EA0 ~ EA12, ETEST1 ~ETEST4, PGMB, ECEB, EOEB, VPP, VDDT, PIE Decoder & Bus Control
DATA Control signals
128 bytes SRAM
DATA
INT
8K-byte EPROM
48 bytes DPRAM LCD Controller LCD Address LCD data LCD Driver SEG0 ~ SEG31
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COM0 ~ COM11
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SPL11A PROGRAMMING GUIDE
3 Memory
3.1 Memory Mapping
$00 ~ $1F
Control Port
$50 ~ $7F
48 bytes LCD RAM
$80 ~ $FF $1E0 ~ $1FF
128 bytes SRAM
$200 ~ $3FF
Reserved
$400 ~ $5FF
Test program
$600 ~ $DFFF
Reserved
$E000 ~ $FFFF
8K bytes ROM/EPROM
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3.2
Memory location
LCD RAM is a dual-port SRAM, from $50 to $7F $0080 ~ $00FF is CPU SRAM; $01E0 ~ $01FF maps to $E0 ~ $FF for the use of stack (maximum stack is 32 bytes). ** The top stacker pointer must be placed in the range of $01E0~$01FF. 8K-byte ROM/EPROM address is from $E000 ~ $FFFF 512-byte test program ROM ($400 ~ $5FF), for Sunplus use only. $FFF9 bit7 is for OTP security if this bit set "1" (data is not readable).
3.3
Vector
Test program interrupt vector: $5FA~$5FF (Sunplus use only). User program interrupt vector: $FFFA~$FFFF.
3.4
Error-address area
Unavailable address range: $0020 ~ $004F, $0100 ~ $01DF, $0200 ~ $03FF, $0600 ~ $DFFF, and $0400 ~ $05FF. Accessing these addresses will cause the entire system to be reset and the b3 (error-address flag) in P_12H_RST_FG ($0012) will be set to "1".
3.5
Example
$FFFA must be added to the following interrupt vectors: DW DW DW NMI RESET IRQ
Initial stack pointer: LDX TXS .............. #FFH
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4 CPU Clock Control
4.1 Clock Source Control
There are two groups of clock sources controlled by two clock option pins: 1. 2. High-speed clock sources (HSCK): PLL / ROSC. Low-speed clock sources (LSCK): 32768Hz oscillator / 32768 Crystal. In OTP version: HSCK
They are selected by pin option (OTP version) or mask option (ROM version).
(High-speed clock) can be selected to PLL or Rosc via HCKOPT pin (pull-high for PLL; pull-low for ROSC (default)). In ROM version: HSCK (High-speed clock) can be selected to PLL or Rosc via mask option. In OTP version: LSCK (Low-speed clock) can be selected to X32K or R32K by LCKOPT pin (pull high for R32K; pull-low for X32K (default)). In ROM version: LSCK (Low-speed clock) can be selected to X32K or R32K via mask option.
4.1.1
Clock sources combination (OTP)
HCKOPT ROSC/X32K ROSC/R32K PLL/X32K 0 0 1 LCKOPT 0 1 X Note
Note: No PLL/R32K combination, it is mapped to PLL/X32K mode
4.2
CPU Clock Control Register
4.2.1
P_05H_CPU_CLK ($0005): set CPU clock
$0005 Name R/W Default b7 b6 b5 b4 b3 b2 R/W 0 b1 R/W 0 b0 R/W 0
CPUCK2 CPUCK1 CPUCK0
Bit Mode CPUCK=HSCK/16 CPUCK=HSCK/8 CPUCK=HSCK/4 CPUCK=HSCK/2 CPUCK=LSCK(32768)
b2 (CPUCK2) 0 0 0 0 1
b1 (CPUCK1) 0 0 1 1 X
b0 (CPUCK0) 0 1 0 1 X
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5 IO and RFC function
5.1 PortA(IOA) Control Register
Relevant Register: P_00H_IOA_Data($0000), P_01H_IOA_Dir($0001), P_02H_IOA_Attrib($0002)
5.1.1
P_00H_IOA_Data ($0000): Data register of PortA
Write data into register and read data back from IOA pad
$0000 Name R/W Default
b7
IOADAT7 R/W 0
b6
IOADAT6 R/W 0
b5
IOADAT5 R/W 0
b4
IOADAT4 R/W 0
b3
IOADAT3 R/W 0
b2
IOADAT2 R/W 0
b1
IOADAT1 R/W 0
b0
IOADAT0 R/W 0
5.1.2
$0001 Name R/W Input Output Default
P_01H_IOA_Dir ($0001): Direction Control register of PortA
b7 IOADIR7 R/W 0 1 0 b6 IOADIR6 R/W 0 1 0 b5 IOADIR5 R/W 0 1 0 b4 IOADIR4 R/W 0 1 0 b3 IOADIR3 R/W 0 1 0 b2 IOADIR2 R/W 0 1 0 b1 IOADIR1 R/W 0 1 0 b0 IOADIR0 R/W 0 1 0
5.1.3
$0002 Name R/W Default
P_02H_IOA_Attrib ($0002): Attribute data register of PortA
b7 IOAATT7 R/W 0 b6 IOAATT6 R/W 0 b5 IOAATT5 R/W 0 b4 IOAATT4 R/W 0 b3 IOAATT3 R/W 0 b2 IOAATT2 R/W 0 b1 IOAATT1 R/W 0 b0 IOAATT0 R/W 0
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SPL11A PROGRAMMING GUIDE Configuration of IOA [7:0], where x represents IOA individual bit. Dir ($01.x) 0 0 0 Attrib ($02.x) Data ($00.x) I/O Identity (IOAx) 0 0 1 0 1 1 Pull Low Pull High LCD output (IO floating) Description Input with pull-low Input with pull-high IOA5 => COM 8 IOA4 => COM 11 IOA3 => SEG29 IOA2 => SEG28 IOA0/IOA1/IOA6/IOA7 are input floating 0 1 0 Pass Through IOA7 => IROUT IOA6 => TONE IOA5 => HSCK/N-TIMER IOA4 => LSCK(32768) IOA0/IOA1/IOA2/IOA3 are output Low 1 1 1 0 0 1 1 0 X Output High Output Low Float Output Data High Output Data Low Input with float
Note 1. IOA6/TONE: IOA6 or TONE (Timer overflow divided by 2). For timer configuration, please refer to the P_09H_TIMER_SET ($0009) in the Timer/Counter for more information. 2. To implement Open drain N-MOS (ODN) and Open drain P-MOS (ODP), do the following:
Open drain N-MOS:
DIR 1
Attrib 1
Data 0
DIR 1
Attrib 0
Data 0
DIR 1
Attrib 1
Data 0
Floating
Output Low
Floating
Open drain P-MOS:
DIR 1
Attrib 1
Data 1
DIR 1
Attrib 0
Data 1
DIR 1
Attrib 1
Data 1
Floating
Output High
Floating
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5.2
Resistor to Frequency Converter (RFC) Function
Because the heat-resistance sensor and moisture-resistance sensor will change its resistance due the change of temperature and humidity, RC time constant will also be changed. this identity to measure temperature or humidity. Programmers can use
5.2.1
P_13H_RFC_CTL ($0013): RFC Control Register
$00013 Name R/W Default b7 b6 b5 b4 b3 b2 b1 b0 RFCEN R/W 0
bit bit0
Name RFCEN
Description 0: RFC function disable 1: RFC function enable
When RFC (Resistor to Frequency Converter) function is enabled by RFCEN=1, we configure one of IOA3 (RREF), IOA4(RTH), IOA5(RTMP) to be pass-through & IOA1 (CX) to be Input-floating to make RFC function.
Set one of these ports to be Output High for each measurement
Input to timer to count RC-pulse number / pulse duration
RFC application circuit
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5.2.2
How to use RFC function
Generate RC pulse Step 1: Set one of IOA3/IOA4/IOA5 ports to be passed-through for each measurement; the other two ports are Input-floating. Step 2: Set IOA1 to Input floating. Step 3: Enable RFC function ($0013 register) to generate RC-Oscillation pulse.
Measurement Long RC time constant: use high-speed clock to sample RC-pulse in P_09H_TIMER_SET($0009) Step 1: GroupA timer-clock source comes from HSCK/N_TIMER (HSCK/N where N is the divisor of HSCK, selected in P_09H_TIMER_SET($0009)) . Step 2: GroupB timer-clock source comes from EXT2 divided by 2 (EXT2CFG=1) Step 3: Sample the number of HSCK pulses in one RC pulse. Short RC time constant: use LSCK divided by M (where M is the divisor of LSCK, selected in P_09H_TIMER_SET($0009) ) as time-base to count RC-pulse in P_09H_TIMER_SET($0009). Step 1: GroupA timer-clock source comes from EXT2. Step 2: GroupB timer-clock source comes from LSCK/M_TIMER (LSCK/M as time-base). Step 3: Count the number of RC pulses in LSCK/M time-base.
5.2.3
Function description of PortA(IOA[7:0])
IOA7 IOA6 IOA5 Schmitt Special Function 1. I/O 2. Pass-through: IROUT 1. I/O 2. Pass-through: TONE 1. I/O 2. Pass-through: HSCK/N_TIMER 3. LCD output: COM8 4. Output pin for RFC application 1. I/O 2. Pass-through: LSCK 3. LCD output: COM11 4. Output pin for RFC application 1. I/O 2. LCD output: SEG29 3. Output pin for RFC application 1. I/O 2. LCD output: SEG28 1. I/O 2. EXT2 interrupt with P/N edge 3. Timer input 4. Input pin for RFC application 1. I/O 2. EXT1 interrupt with P/N edge 3. Timer input
IOA4
-
IOA3 IOA2 IOA1
Yes
IOA0
Yes
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SPL11A PROGRAMMING GUIDE Note: IOA[1:0] Input with Schmitt Trigger. When IOA is used for COM or SEG, read operation will always return "low". on IOA besides COM and SEG, pad status can be read back. For other settings
5.2.4
IOA Structure
IOA[1:0]
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SPL11A PROGRAMMING GUIDE IOA[7:2]
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5.3
PortB(INB) Control Register
INB[7:0]: Input Only with pull-low & wakeup function Relevant Registers: P_03H_INB_Data ($0003), P_10H_IO_Config ($0010)
5.3.1
P_03H_INB_Data ($0003)
Write to latch INB data for key-change function and read data from INB pad.
$0001 Name R/W Default
b7 INBDAT7 R/W 0
b6 INBDAT6 R/W 0
b5 INBDAT5 R/W 0
b4 INBDAT4 R/W 0
b3 INBDAT3 R/W 0
b2 INBDAT2 R/W 0
b1 INBDAT1 R/W 0
b0 INBDAT0 R/W 0
5.3.2
P_10H_IO_Config ($0010)
Configuration register of INB & IOA
$0001 Name R/W Default
b7 EXT2EDG R/W 0
b6 EXT1EDG R/W 0
b5 INBSET5 R/W 0
b4 INBSET4 R/W 0
b3 INBSET3 R/W 0
b2 INBSET2 R/W 0
b1 INBSET1 R/W 0
b0 INBSET0 R/W 0
Bit b0 b1 b2 b3 b4 b5 b6 b7
Name INBSET0 INBSET1 INBSET2 INBSET3 INBSET4 INBSET5 EXT1EDG EXT2EDG
Description 0: INB0 input with pull-low; 1: INB0 input with pull-high 0: INB1 input with pull-low; 1: INB1 input with pull-high 0: INB2 & INB3 input with pull-low; 1: INB2 & INB3 input with pull-high 0: INB4 ~ INB7 input with pull-low; 1: INB4 ~ INB7 input with pull-high 0: INB3=INB3; 1: INB3 as LCD output (SEG30/COM9) 0: INB4=INB4, 1: INB4 as LCD output (SEG31/COM10) 0: IOA0 (EXT1) falling edge interrupt; 1: IOA0 (EXT1) rising edge interrupt 0: IOA1 (EXT2) falling edge interrupt; 1: IOA1 (EXT2) rising edge interrupt For other settings on
Note: When INB is used for COM or SEG, the read operation will always return "low". INB besides the COM and SEG, the pad status can be read back.
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5.3.3
INB Structure
INB[7:3]
INB[2:0]
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6 System Control
6.1 System Control
6.1.1 P_0FH_SYS_SWITCH ($000F)
Set the system operation mode, and it is a two write-operation port. (1). First write: write $000F register with correct patterns (PAT[6:0])
BIT7
X
BIT6
PAT6
BIT5
PAT5
BIT4
PAT4
BIT3
PAT3
BIT2
PAT2
BIT1
PAT1
BIT0
PAT0
(2). Second write: write $000F register with Data-bit and correct patterns (PAT[6:0]) to set function-bit.
BIT7
DATA
BIT6
PAT6
BIT5
PAT5
BIT4
PAT4
BIT3
PAT3
BIT2
PAT2
BIT1
PAT1
BIT0
PAT0
Data to set function bit
PATTERN st 1 Write: X0000001 nd 2 Write: D0001110 D: 0 Normal; 1 Wait Mode HSCK Control 1st Write : X0000010 nd 2 Write : D0001101 D : 0 Turn-ON; 1 Turn-OFF LSCK Control 1st Write : X0000011 nd 2 Write : D0001100 D : 0 Turn-ON; 1 Turn-OFF st Watchdog 1 Write: X0000100 nd clear 2 Write: D0001011 Control D: 0 No-Clear; 1 Clear WDOG st X32K mode 1 Write: X0000101 nd Control 2 Write: D0001010 D: 0 weak mode 1 strong mode st Wakeup 1 Write: X0000110 nd Control 2 Write: D0001001 D: 0 Wakeup to CPU-Reset 1 Wakeup to Next-instruction FUNCTION WAIT mode Control COMMENT Stop CPU clock only, HSCK/LSCK sources are still ON If CPU clock is from HSCK, STOP HSCK system enter Halt mode (LSCK is still ON) Stop LSCK system enter Standby mode
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6.1.2
P_0FH_SYS_SWITCH ($000F)
System state read back BIT b0 b1 b2 b3 b4 b5 b6 b7 READ FROM P_0FH_SYS_SWITCH ($000F) STATUS 0:HSCk is still ON 1:HSCK is OFF 0:LSCK is in weak mode 1:LSCK is in strong mode 0:Wakeup to CPU-Reset 1:Wakeup to next-instruction N/A N/A N/A N/A N/A
Description: 1. The P_0FH_SYS_SWITCH ($000F) is a two-stage control port. A successful writing of the first stage makes the 2 2.
nd nd
stage to be valid.
Firmware must write to setup this port in the 2
stage.
The b7 is the data bit for the second stage writing operation. The X32K crystal initially starts running at strong mode and will change to weak mode after 250ms automatically when X32K crystal is turned on (This will not change the setting in $0F weak/strong mode setting). Program will be executed after crystal oscillation is stabilized. 3. 4. 5. 6. Using PLL for IR or Timer source, user's program must delay at least 8ms for the stabilization of the PLL circuit at the moment of PLL start running. If no any wakeup source is configured, it is unable to enter WAIT/HALT/STANDBY mode. Setting WAIT/HSCK/LSCK control bit to enter WAIT/HALT/STANDBY mode. Waking up from standby mode, the P_05H_CPU_CLK ($0005) will be reset to the default value (HSCK/16). state. In wait and halt modes, the P_05H_CPU_CLK ($0005) will remain the same
Mode Operating WAIT HALT STANDBY
Description Normal operating mode CPU OFF / all clock sources are still ON
Action --Configure $0F register to set WAIT mode.
CPU OFF/ HSCK OFF, 32768 Configure $0F register to stop HSCk when still ON CPU OFF/All clock-sources OFF CPU clock is HSCK. Configure $0F register to stop LSCK regardless where the CPU clock comes from HSCK or LSCK.
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OPERATING
Write $0F Set WAIT
Write $0F Disable LSCK
CPUCK= HSCK YES
NO
Write $0F Disable HSCK
Write $0F Disable HSCK
WAIT-mode
STANDBY-mode
HALT-mode
Operating-mode stop HSCK only
6.2
Reset Flags
6.2.1
$00012 Name R/W Default
P_12H_RST_FG ($0012)
b7 b6 b5 b4 LVR R 0 b3 IAR R 0 b2 WDOG R 0 b1 RESETP R 0 b0 POR R 0
b0: Power on reset b1: External pin reset b2: Watchdog reset b3: Error-address reset b4: Low voltage reset
Note: 1. All reset flags can be cleared by reading $12. 2. Power-on reset & external pin reset will reset low-voltage, watchdog, and error-address reset. 3. Power-on reset, external pin reset, and low voltage reset will reset entire system (all ports also are reset). Others reset functions only reset CPU (ports will not be reset).
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7 Timer/Counter
7.1 Timer Structure
EXT2/IOA1
HSCK HSCK/N_Timer EXT1/IOA0 VDD MUX Group A
AND
LSCK LSCK/M_Timer EXT2/2 EXT2/ or IOA1 VDD MUX Group B
16-bit reloadable timer/ P/N Edge Count TMO/INT
TONE/IOA6 /2
7.2
Timer Setup & Initialization
7.2.1 P_09H_TIMER_SET ($0009): Set the timer/counter configuration
b7 TMREN R/W 0 b6 TEDGE R/W 0 b5 EXT2CFG R/W 0 b4 TCKB1 R/W 0 b3 TCKB0 R/W 0 b2 TCKA2 R/W 0 b1 TCKA1 R/W 0 b0 TCKA0 R/W 0
$0009 Name R/W Default
Timer-Clock setting groupA Bit CLK source HSCK HSCK/N_TIMER EXT1 VDD EXT2 Note: 1. 2. HSCK/N_TIMER is HSCK/N clock source set by P_0CH_Timer_INT1 ($000C). EXT1: rising or falling edge interrupt from IOA0 with Glitch-Filter. b2 (TCKA2) 0 0 0 0 1 b1 (TCKA1) 0 0 1 1 X b0 (TCKA0) 0 1 0 1 X
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Timer-Clock setting groupB bit CLK source LSCK LSCK/M_TIMER EXT2 VDD Note: 1. 2. LSCK/M_TIMER is LSCK/M clock source set by P_0DH_Timer_INT2 ($000D). EXT2: Rising or falling edge interrupt from IOA1 with Glitch-Filter and Ext2 can be used as RC-pulse input in RFC function. b4 (TCKB1) 0 0 1 1 b3 (TCKB0) 0 1 0 1
Bit b5 b6 b7
Name
Description 1: EXT2 divided by 2 (as Timer-clock)
EXT2CFG 0: EXT2 (as Timer-clock) TEDGE TMREN 0: falling edge up-count 1: rising edge up-count 0: Disable Timer 1: Enable Timer
7.3
Timer/Interrupt Clock Sources
A. HSCK sources for timer, interrupt 7.3.1 P_0CH_TIMER_INT1 ($000C)
Set HSCK/N as the Timer/Interrupt input source
$000C Name R/W Default
b7 -
b6 -
b5 -
b4 LINT1 R/W 0
b3 LINT0 R/W 0
b2 LTIM2 R/W 0
b1 LTIM1 R/W 0
b0 LTIM0 R/W 0
HSCK/N Clock for Timer: bit HSCK/N_Timer 37.9K/16 37.9K/8 b2 (LTIM2) b1 (LTIM1) b0 (LTIM0)
0 0
0 0
0 1
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bit HSCK/N_Timer 37.9K/4 37.9K/2 37.9K HSCK/8 HSCK/4 HSCK/2
b2 (LTIM2)
b1 (LTIM1)
b0 (LTIM0)
0 0 1 1 1 1
1 1 0 0 1 1
0 1 0 1 0 1
HSCK/N Clock for Interrupt bit HSCK/N_INT 37.9K/16 37.9K/8 37.9K/4 37.9K/2 b4 (LINT1) 0 0 1 1 b3 (LINT0) 0 1 0 1
B. LSCK(32768) sources for timer, interrupt sources 7.3.2 P_0DH_TIMER_INT2 ($000D)
Set 32768Hz/M as the Timer/Interrupt input source where M is frequency divisor. $000D Name R/W Default b7 b6 32KINT2 R/W 0 b5 32KINT1 R/W 0 b4 32KINT0 R/W 0 b3 RTC R/W 0 b2 32KTIM2 R/W 0 b1 32KTIM1 R/W 0 b0 32KTIM0 R/W 0
LSCK/M clock for Timer: b2 LSCK/M_Timer 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz 128 Hz 1024 Hz 4096 Hz (32KTIM2) 0 0 0 0 1 1 1 1 b1 (32KTIM1) 0 0 1 1 0 0 1 1 b0 (32KTIM0) 0 1 0 1 0 1 0 1
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Real-Time Clock setting Bit b3 Name RTC Description 0: 2 Hz 1: 1 Hz
LSCK/M clock for Interrupt: LSCK/M_INT 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz 128 Hz 1024 Hz 4096 Hz b6 (32KINT2) 0 0 0 0 1 1 1 1 b5 (32KINT1) 0 0 1 1 0 0 1 1 b4 (32KINT0) 0 1 0 1 0 1 0 1
7.4
Timer Data Register
7.4.1 P_0AH_TML_LATCH ($000A)
Set/load timer data into Timer b7 ~ b0 (low byte).
$000A Name R/W Default
b7 TMLL7 R/W 0
b6 TMLL6 R/W 0
b5 TMLL5 R/W 0
b4 TMLL4 R/W 0
b3 TMLL3 R/W 0
b2 TMLL2 R/W 0
b1 TMLL1 R/W 0
b0 TMLL0 R/W 0
7.4.2
P_0BH_TMH_LATCH ($000B)
Set/load timer data into Timer b15 ~ b8 (high byte).
$000B Name R/W Default
b7 TMHL7 R/W 0
b6 TMHL6 R/W 0
b5 TMHL5 R/W 0
b4 TMHL4 R/W 0
b3 TMHL3 R/W 0
b2 TMHL2 R/W 0
b1 TMHL1 R/W 0
b0 TMHL0 R/W 0
Note. 1. 16-bit reloadable rising or falling edge up-count Timer/Counter 2. When preloaded value is loaded into Timer, write P_0AH_TML_Latch first and next write P_0BH_TMH_Latch to load timer data to timer.
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8 LCD
8.1 LCD RAM mapping
SEG0~SEG7 b0~b7 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 $50 $54 $58 $5C $60 $64 $68 $6C $70 $74 $78 $7C SEG8~SEG15 b0~b7 $51 $55 $59 $5D $61 $65 $69 $6D $71 $75 $79 $7D SEG16~SEG23 b0~b7 $52 $56 $5A $5E $62 $66 $6A $6E $72 $76 $7A $7E SEG24~SEG31 b0~b7 $53 $57 $5B $5F $63 $67 $6B $6F $73 $77 $7B $7F
8.2
Control registers
LCD related register: P_04H_LCD_CTL ($0004), P_11H_LCDCK_CTL ($0011)
8.2.1
Port_LCD_CTL ($0004)
LCD Control register $0004 Name R/W Default b7 R/W 0 b6 R/W 0 b5 R/W 0 b4 R/W 0 b3 BIAS0 R/W 0 b2 R/W 0 b1 R/W 0 b0 R/W 0
PUMPCK LCDMOD1 LCDMOD0 BIAS1
DUTY2 DUTY1 DUTY0
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SPL11A PROGRAMMING GUIDE Duty Control of LCD BIT Mode 1/3 Duty 1/4 Duty 1/5 Duty 1/8 Duty 1/9 Duty 1/10 Duty 1/11 Duty 1/12 Duty 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 b2 (DUTY2) b1 (DUTY1) b0 (DUTY0)
Bias Control of LCD bit Mode 1/2 Bias 1/3 Bias 1/4 Bias Note: 1. If 1/4 bias is selected, the pins of V3_INB5, CPU3_INB6 and CPU4_INB7 will not perform as ordinary I/O functions; instead, they are used for V3, CPU3 and CPU4 for bias circuit. these pins are used for I/O purpose. 2. When duty is over 1/8, Sunplus recommends using 1/4 bias for LCD quality improvement. For 1/2 and 1/3 bias options, b4 (BIAS1) 0 0 1 b3 (BIAS0) 0 1 X
LCD operating mode BIT Mode LCD OFF NORMAL All dots ON All dots OFF 0 0 1 1 0 1 0 1 b6 (LCDMOD1) b5 (LCDMOD0)
Default: LCD off, meaning both common and segment are remained low.
LCD pump clock control Bit Mode Pump clock = 8K Pump clock = 32K
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b7 (PUMPCK) 0 1
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SPL11A PROGRAMMING GUIDE Note: Wait bias setting to be stabilized (a completed frame) and next turn the LCD on. Note 2: LCD off voltage, SEG = Low (0V) & COM = Low (0V)
8.2.2
LCD clock control
Port_LCDCK_CTL ($0011): LCD clock control register; tune LCD frame-rate with smaller step. $0011 Name R/W Default b7 b6 b5 b4 b3 LCK3 R/W 0 b2 LCK2 R/W 0 b1 LCK1 R/W 0 b0 LCK0 R/W 0
Frame-rate tuning range: approx. 40Hz ~ 100Hz with different steps for various duties For 1/3 bias, 1/4bias, and 1/5bias: BIT[3:0] (LCK[3:0]) 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 1/3 bias N/A N/A N/A N/A N/A N/A 97.5 85.3 75.8 68.3 62.1 56.9 52.5 48.8 45.5 42.7 Frame Rate(Hz) 1/4 bias N/A N/A N/A N/A 102.3 85.3 73.1 64.0 56.9 51.2 46.6 42.7 39.4 N/A N/A N/A 1/5 bias N/A N/A N/A 102.4 81.9 68.3 58.5 51.2 45.5 41.0 N/A N/A N/A N/A N/A N/A
NA: Sunplus recommends not to give any value to the b[3:0]
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SPL11A PROGRAMMING GUIDE For 1/8 bias~1/12 bias BIT[3:0] (LCK[3:0]) 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 1/8 bias NA NA NA NA 102.4 85.3 73.2 64.0 56.9 51.2 46.5 42.7 39.4 NA NA NA 1/9 bias NA NA NA NA 91.0 75.9 65.0 56.9 50.6 45.5 41.4 37.9 NA NA NA NA Frame Rate(Hz) 1/10 bias NA NA NA 102.4 81.9 68.3 58.5 51.2 45.5 41.0 NA NA NA NA NA NA 1/11 bias NA NA NA 93.1 74.5 62.1 53.2 46.5 41.4 NA NA NA NA NA NA NA 1/12 bias NA NA NA 85.3 68.3 56.9 48.8 42.7 NA NA NA NA NA NA NA NA
NA: Sunplus recommends not to give any value to the b[3:0].
8.3
Multiple functions (I/O, segment & common sharing)
8.3.1
LCD dots 360 dots (12 x 30) 330 dots (11 x 30) 300 dots (10 x 30) 288 dots (9 x 32) 256 dots (8 x 32) 160 dots (5 x 32) 128 dots (4 x 32) 96 dots (3 x 32)
LCD dot & I/O
IO Used INB0 ~ INB2, IOA0, IOA1, IOA6, IOA7 INB0 ~ INB2, IOA0, IOA1, IOA4, IOA6, IOA7 INB0~INB2, INB4, IOA0, IOA1, IOA4, IOA6, IOA7 INB0 ~ INB2, IOA0, IOA1, IOA4, IOA6, IOA7 (3 Input & 5 IO) INB0 ~ INB2, IOA0, IOA1, IOA4 ~ IOA7 (3 Input & 6 IO) INB0 ~ INB3, INB5 ~ INB7, IOA0 ~ IOA7 (7 Input & 8 IO) INB0 ~ INB7, IOA0 ~ IOA7 (8 Input & 8 IO) INB0 ~ INB7, IOA0 ~ IOA7 (8 Input & 8 IO)
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8.3.2
Dots Signals COM[0:2] COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 SEG28 SEG29 SEG30 SEG31
LCD mapping with dot resolution
288 dots (9 x 32) COM[0:2] COM3 COM4_ SEG31 COM5_ SEG30 COM6_ SEG29 COM7_ SEG28 IOA5 IOA2 IOA3 INB3 INB4 300 dots (10 x 30) COM[0:2] COM3 COM4_ SEG31 COM5_ SEG30 COM6_ SEG29 COM7_ SEG28 IOA5 INB3 SEG[0:27] IOA2 IOA3 330 dots (11 x 30) COM[0:2] COM3 COM4_ SEG31 COM5_ SEG30 COM6_ SEG29 COM7_ SEG28 IOA5 INB3 INB4 SEG[0:27] IOA2 IOA3 360 dots (12 x 30) COM[0:2] COM3 COM4_ SEG31 COM5_ SEG30 COM6_ SEG29 COM7_ SEG28 IOA5 INB3 INB4 IOA4 SEG[0:27] IOA2 IOA3 -
96 dots (3 128 dots 160 dots 256 dots x 32) COM7_ SEG28 COM6_ SEG29 COM5_ SEG30 COM4_ SEG31 (4 x 32) COM3 COM7_ SEG28 COM6_ SEG29 COM5_ SEG30 COM4_ SEG31 (5 x 32) COM3 COM4_ SEG31 COM7_ SEG28 COM6_ SEG29 COM5_ SEG30 INB4 INB4 INB3 IOA3 (8 x 32) COM3 COM4_ SEG31 COM5_ SEG30 COM6_ SEG29 COM7_ SEG28 IOA2 COM[0:2] COM[0:2] COM[0:2] COM[0:2]
SEG[0:27] SEG[0:27] SEG[0:27] SEG[0:27] SEG[0:27] SEG[0:27]
: indicates physical pin on the chip. EX: In 96 dots matrix, the signal of SEG31 is outputted from COM4_SEG31. EX: In 160 dots matrix, the signal of COM4 is outputted from COM4_SEG31.
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9 Wakeup / Interrupt
9.1 Wakeup/Interrupt Structure Diagram
P__0EH_INT_SET ($000E) Set the enabled WKU sources can be used as Interrupt
INT7
WKU7
INT6
INTS7
INTS6
INTS5
INTS4
INTS3
INTS2
INTS1
INTS0
WKU6
INT5
WKU5
INT4
WKU4
INT3
INT2
WKU3
INT1
WKU2
INT0
WKU1
WKU0
WKU7
TMO
WKU6
KEYC
WKU5
TMO
WKU4
32K/M_INT
WKU3
PLL/N_INT
WKU2
T2HZ
WKU1
EXT2
WKU0
EXT1
WKUS7
WKUS6
WKUS5
WKUS4
WKUS3
WKUS2
WKUS1
WKUS0
WKUC6
P_07H_WKU_SET ($0007) Write to enable WKU source Readback which WKU occurs
WKUC5
WKUC4
WKUC3
WKUC2
WKUC1
WKUC0
P_08H_WKU_CLR ($0008)
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9.2
Wakeup/Interrupt Control registers
Related registers: P_07H_WKU_SET ($0007), P_08H_WKU_CLR ($0008), P_0EH_INT_SET($000E)
9.2.1
P_07H_WKU_SET ($0007)
Write register to enable/disable wakeup sources bit by bit and identify which wakeup source occurs.
$0007 Name R/W Default
b7 WKUS7 R/W 0
b6 WKUS6 R/W 0
b5 WKUS5 R/W 0
b4 WKUS4 R/W 0
b3 WKUS3 R/W 0
B2 WKUS2 R/W 0
b1 WKUS1 R/W 0
b0 WKUS0 R/W 0
Bit b0 b1 b2 b3
Name WKUS0 WKUS1 WKUS2 WKUS3
Description Wakeup source: EXT1(IOA0); Wakeup source: EXT2(IOA1); 0: disabled, 1: enabled 0: disabled, 1: enabled Falling (default)/Rising edge from IOA0 (set by Port_IO_Config($0010), b6) Falling (default)/Rising edge from IOA1 (set by Port_IO_Config($0010), b7) Wakeup source: 2Hz or 1Hz (set by P_0DH_Timer_INT2($000D), b3 ) 0: disabled, 1: enabled Wakeup source: HSCK/N_INT (37.9KHz divided by 2/4/8/16, set by P_0CH_Timer_INT1 ($000C), b[4:3]) 0: disabled, 1: enabled
b4 b5 b6 b7
WKUS4 WKUS5 WKUS6 WKUS7
Wakeup source: LSCK/M_INT (4096/1024/128/64/32/16/8/4 Hz, set by P_0DH_Timer_INT2($000D), b[6:4] ) ; Wakeup source: Timer Overflow IRQ 0: disabled, 1: enabled Wakeup source: key change (INB[7:0]) 0: disabled, 1: enabled 0: Timer overflow NMI disabled (timer overflow as IRQ) 1: Timer overflow NMI enabled (WKUS5 will be auto-disabled) Read for checking NMI occurrence. 0: disabled, 1: enabled
Note: 1. 2. When WKUC5 clears TMO (timer overflow), it will also clear WKU7 (NMI). The WKUS7 configures TMO as IRQ (WKUS7=0) or NMI (WKUS7=1). NMI (WKUS7=1), WKUC5 (TMO IRQ) will be disabled automatically. If WKUS7 is configured TMO as
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9.2.2
$0008 Name R/W Default
Port_WKU_CLR ($0008)
b7 b6 WKUC6 W 0 b5 WKUC5 W 0 b4 WKUC4 W 0 b3 WKUC3 W 0 b2 WKUC2 W 0 b1 WKUC1 W 0 b0 WKUC0 W 0
Bit b0 b1 b2 B3 B4 B5 b6 b7 Note 1.
Name WKUC0 WKUC1 WKUC2 WKUC3 WKUC4 WKUC5 WKUC6 -
Description Clear Wakeup source: EXT1(IOA0) Clear Wakeup source: EXT2(IOA1) Clear Wakeup source: 2Hz or 1Hz (set by P_0DH_Timer_INT2($000D), Bit3 ) Clear Wakeup source: HSCK/N_INT (37.9KHz divided by 2/4/8/16, set by P_0CH_Timer_INT1($000C), Bit[4:3]) Clear Wakeup source: LSCK/M_INT(4096/1024/128/64/32/16/8/4 Hz, set by P_0DH_Timer_INT2($000D), Bit[6:4] ) Clear Wakeup source of Timer Overflow The clearance will also clear both TMO IRQ & NMI. Clear Wakeup source: Key change wakeup (INB[7:0]) N/A
All interrupts will wake CPU up and execute program from reset or next instruction (see PORT_SYS_SWITCH).
2.
Write data into this register will clear both wakeup and interrupt flags.
9.2.3
P_0EH_INT_SET($000E)
Set wakeup sources as interrupt
$000E Name R/W Default
b7 INTS7 R/W 0
b6 INTS6 R/W 0
b5 INTS5 R/W 0
b4 INTS4 R/W 0
b3 INTS3 R/W 0
b2 INTS2 R/W 0
b1 INTS1 R/W 0
b0 INTS0 R/W 0
bit b0 b1 b2
Name INTS0 INTS1 INTS2
Description 0: EXT1 is used for wakeup source only. 1: EXT1 is used for both wakeup & IRQ 0: EXT2 is used for wakeup source only. 1: EXT2 is used for both wakeup & IRQ. 0: 2Hz or 1Hz is used for wakeup source only. 1: 2Hz or 1Hz is used for both wakeup & IRQ.
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b3 b4 b5 b6 b7
INTS3 INTS4 INTS5 INTS6 INTS7
0:HSCK/N_INT is used for wakeup source only. 1: HSCK/N_INT is used for both wakeup $ IRQ. 0: LSCK/M_INT is used for wakeup source only. 1: LSCK/M_INT is used for both wakeup & IRQ. 0: TMO is used for wakeup source only. 1: TMO is used for both wakeup & IRQ. 0: Key-change is used for wakeup source only. 1: Key-change is used for both wakeup and IRQ. 0: TMO NMI is used for wakeup source only. 1: TMO NMI is used for both wakeup & NMI.
Notice: Suppose the wakeup source is used for IRQ and also if the program executes from reset after wakeup is accepted, IRQ will not be generated till a CLI instruction is met. interrupt flag (I) when reset operation is performed. The reason is that CPU will set the CPU internal
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10 Remote Control
10.1 Control registers
10.1.1 P_06H_DUTY_CTL ($0006)
IROUT control register $0006 Name R/W Default b7 b6 b5 b4 IREN R/W 0 b3 IRCTL R/W 0 b2 IRDTY2 R/W 0 b1 IRDTY1 R/W 0 b0 IRDTY0 R/W 0
IROUT pulse duty control Bit Mode 0/8 Duty 1/8 Duty 2/8 Duty 3/8 Duty 4/8 Duty 5/8 Duty 6/8 Duty 7/8 Duty Note: 1/8 Duty b2 (IRDTY2) 0 0 0 0 1 1 1 1 1/8 duty high, 7/8 duty Low b1 (IRDTY1) 0 0 1 1 0 0 1 1 b0 (IRDTY0) 0 1 0 1 0 1 0 1
Bit b3 b4 Note:
Name IRCTL IREN
Description 0: Software control IROUT 1: Timer overflow for IROUT 0: IROUT=0 1: IROUT=37.9KHz
For the initialization of using timer overflow as the IR control, setting IREN=0 first and then setting IREN=1 will generate a 37.9KHz signal at the first timer overflow occurrence. In
contrast, if setting IREN=0, but not setting IREN back to "1", the 37.9KHz will not be generated at any time.
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11 Development System
The SPL11A development system consists of a simulator, OTP writer with a COB/QFP package, and demo board.
11.1
SPL11A Simulator
The SPL11A development system includes a simulator (see figure below) to emulate the functionality of SPL11A, developed by programmer. For more information about how to use this simulator, please
refer to SPL11A simulator User's Manual.
Caution: After user's program is fully tested on the simulator, testing on SPL11A OTP demo board is also required to ensure the functionality.
11.2
OTP Writer and demo board
The SPL11A development should also include an OTP writer to program SPL11A OTP chip and a demo board to demonstrate the designed functions. For more information about how to program the SPL11A OTP and use of demo board, please refer to Sunplus OTP/MTP Writer User's Manual.
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12 Mask/Bonding option
12.1 Mask options for ROM version of SPL11A
PLL or Rosc X32K or R32K Low voltage reset enable or disable
12.2
Bonding options for OTP version of SPL11A
Option Pin Name HCKOPT LCKOPT LVROFF Bonding Low (No Bonding) Bonding High Description
Rosc
32K crystal Low voltage reset on
PLL
32K Rosc Low voltage reset off
----Low voltage reset at 2.4V
12.3
Default status of pins
Pin IOA (IOA0 ~ IOA7) INB (IOB0 ~ IOB7) CUP3/INB6 CUP4/INB7 V3/INB5 COM4/SEG31 COM5/SEG30 COM6/SEG29 COM7/SEG28 INB3/SEG30/COM9 INB4/SEG31/COM10 IOA4/COM11 IOA5/COM8 VCOIN/ROSC X32I/R32I Default state Input with pull-low Input with pull-low INB6 (determined by bias) INB7 (determined by bias) INB5 (determined by bias) SEG31 (determined by duty) SEG30 (determined by duty) SEG29 (determined by duty) SEG28 (determined by duty) INB3 (determined by duty) INB4 (determined by duty) IOA4 (determined by duty) IOA5 (determined by duty) ROSC (HCKOPT =Low) in OTP version X32I (LCKOPT =Low) in OTP version.
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13 Appendix
13.1 Port and Memory Map
Port Address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0020 ~ $004F $0050 ~ $007F $0080 ~ $00FF $0100 ~ $01DF $01E0 ~ $01FF $0400 ~ $05FF $0600 ~ $1FFF $E000 ~ $FFFF $FFF9 Description P_00H_IOA_Data P_01HIOA_Dir P_02H_IOA_Attrib P_03H_INB_Data P_04H_LCD_CTL P_05H_CPU_CLK P_06H_DUTY_CTL P_07H_WKU_SET P_08H_WKU_CLR P_09H_TIMER_SET P_0AH_TML_LATCH P_0BH_TMH_LATCH P_0CH_TIMER_INT1 P_0DH_TIMER_INT2 P_0EH_INT_SET P_0FH_SYS_SWITCH P_10H_IO_CONFIG P_11H_LCDCK_CTL P_12H_RST_FLG P_13H_RFC_CTL Error Address 1 DPRAM for LCD display 128 Byte SRAM for data & stack Error Address 2 32 Byte SRAM for stack (the same SRAM in $00E0 ~ $00FF) Testing Program for Sunplus use only. Error Address 4 in normal mode Error Address 3 8K EPROM Secure option (bit 7)
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13.2
OTP (QFP) PIN Description
Mnemonic SEG27 - 21 SEG20 - 6 SEG5 - 0 COM4_SEG31 COM5_SEG30 COM6_SEG29 COM7_SEG28 COM3 - 0 V1 V2 CUP1 CUP2 IOA7 IOA6 IOA5 PIN No. 13 - 19 25 - 39 44 - 49 8 9 10 11 49 - 52 53 54 55 56 72 73 74 I/O I/O I/O IOA port bit7, can be used to output IR carrier IOA port bit6, can be used to output tone IOA port bit5, shared pin with LCD common8 In RFC application, used as a pass-through (output) pin and connected to sensor. IOA4 75 I/O IOA port bit4, shared pin with LCD common11 In RFC application, used as a pass-through (output) pin and connected to sensor IOA3 76 I/O IOA port bit3, shared pin with LCD segment29 In RFC application, used as a pass-through (output) pin and connected to sensor. IOA2 IOA1 77 78 I/O I/O IOA port bit2, shared pin with LCD segment28. IOA port bit1, Timer external input 2, External Interrupt input 2. In RFC application, used as input-floating pin and connected to sensor & capacitor. IOA0 CUP3_INB7 CUP4_INB6 V3_INB5 INB4 79 57 58 65 7 I/O I I I I/O IOA port bit0, Timer external input 1, External Interrupt input 1 Shared pin for (1) INB input port bit7 with key-change detection detection detection detection (2) Input for setting LCD bias (CUP3). (2) Input for setting LCD bias (CUP4). (2) Input for setting LCD bias (V3). (2) LCD segment 31 (3) LCD common 10. Shared pin for (1) INB input port bit6 with key-change Shared pin for (1) INB input port bit5 with key-change Shared pin for (1) INB input port bit4 with key-change I Inputs for setting LCD bias O O O O O I Shared pin for LCD common4 or segment31 Shared pin for LCD common5 or segment30 Shared pin for LCD common6 or segment29 Shared pin for LCD common7 or segment28 LCD driver common output Inputs for setting LCD bias Type O Description LCD driver segment output.
Sunplus Technology Co., Ltd.
PAGE 41
V0.1 - OCT. 23, 2002
PRELIMINARY
SPL11A PROGRAMMING GUIDE
Mnemonic INB3 INB2 INB1 INB0 LVROFF VDDT VPP PIEP X32I X32O LCKOPT HCKOPT RESETB VSS OSCPLL VDD TEST
PIN No. 6 5 4 3 1 23 24 40 51 52 61 62 66 69 70 71 80
Type I/O I I I I P P I I O I I I P I P I
Description Shared pin for (1) INB input port bit3 with key-change detection (2) LCD segment 30 (3) LCD common 9. INB input port bit2 with key-change detection INB input port bit1 with key-change detection INB input port bit0 with key-change detection LVR (Low-voltage reset) disable pin EPROM testing power EPROM programming power EPROM parallel interface enable 32.768KHz Crystal/R-OSC Input (option) 32.768KHz crystal output Option pin for Low-speed clock selection 0: 32768 crystal; 1: 32768 R-oscillator Option pin for high-speed clock selection 0: R-oscillator; 1: 4.85MHz PLL External reset input pin (Low active) Ground input PLL Input/R-OSC Input (option) Power input Test input
Legend: I = Input, O = Output, P = Power
Sunplus Technology Co., Ltd.
PAGE 42
V0.1 - OCT. 23, 2002

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